Where is the AI Infrastructure Bottleneck?
A continuously updated research operating system tracking where physical constraints emerge, how hyperscaler CapEx migrates across the silicon-to-grid stack, and which monopoly tollbooths extract surplus value.
01 — AI Infrastructure Master Map (10 Layers)
Click any physical layer to inspect active constraints, key companies, and falsifiable theses.
Compute
Accelerators, Hyperscale ASICs & Host Silicon
Memory
High-Bandwidth Stacking & Low-Latency Buffers
Advanced Packaging
Substrates, Interposers & Multi-Die Integration
Semiconductor Equipment
Metrology, Precision Thinning & Advanced Bonding
Networking
Scale-Up NVLink Fabrics & Scale-Out InfiniBand/Ethernet
Optical
Transceivers, Optical Engines & Silicon Photonics
Storage
Check-pointing Tiers & High-Throughput KV Caches
Power
54V/48V Busbars, VRM Power Stages & Power Shelves
Cooling
Direct-to-Chip Cold Plates, CDUs & Fluid Distribution
Grid
Step-Up Transformers, Substations & Utility Interconnection
02 — Active Investment Theses
Core macro & micro-architectural hypotheses with explicit falsification conditions.
AI Memory Super Cycle: HBM4 Turnkey Pricing & Standard DRAM Squeeze
“AI accelerators are increasing memory bandwidth and capacity requirements at an exponential rate. Producing 1 Gb of HBM consumes ~3x the wafer area of standard DDR5. With HBM4 requiring TSMC 3nm / SF 4nm custom base dies, memory is transitioning into custom compute with contract pricing locked at $4.50–$4.90/Gb, establishing structural gross margin durability.”
28-Layer ABF Substrates: The Hidden Packaging Ceiling Behind CoWoS
“While Wall Street models CoWoS wafer limits, the actual binding physical constraint has quietly shifted to Ajinomoto Build-up Film (ABF) substrates. Large-form-factor (>100mm) multi-chip modules suffer from CTE thermal warpage during vacuum lamination, dropping yields to 48–54% and extending lead times past 70 weeks.”
120kW+ Rack Thermal Industrialization & CDU Tollbooths
“NVL72 rack-scale delivery has crossed the industrialization chasm with 99.4% zero-leak certification in 24-hr pressure loops. Shipping 900+ liquid-cooled racks per month at ~$3.1M each requires upwards of $2.5B in rolling working capital, creating an impenetrable oligopoly for Foxconn while cementing Vertiv's CDU lead-time tollbooth.”
03 — Hardware Alpha Coverage
Evaluated by Alpha Score (100), Value Density, and Physical Constraint Exposure.
04 — Research Dispatches & Evidence
The empirical backing supporting our theses and bottleneck calculations.
The Pacific Hardware Tape (#4): Samsung's ₩10.8T Memory Print, HBM4 Price Shock ($4.90/Gb) & 120kW Liquid Cooling
Seoul checks confirm memory margins breached 40% as standard DRAM inventories plunged below 10 days. Opening 2027 contract quotes for HBM4 surged to $4.50–$4.90/Gb (>3x HBM3e levels). Foxconn/CCI completed 24-hr pressure loop tests with 99.4% zero-leak yields on 120kW racks. 28-layer ABF substrate lead times blowout to 56–78 weeks.
The Pacific Hardware Tape (#3): Lisa Su's 5-Year East Asia LTA Blitz, 28-Layer ABF Substrate Queues Hit 78 Weeks & Disco's 30µm Grinding Monopoly
AMD CEO travels through Taipei, Kyoto, and Seoul to secure 5-year packaging allocations. Disco sub-1.5µm total thickness variation (TTV) commands 80%+ gross margin bridge for 3D stacking. Ibiden institutes customer quota rationing.